Microelectronic devices have specific power and current demands, typically at low voltages and across a broad frequency range. A power distribution network is configured to distribute power and ground voltages to all devices in chip circuit and multi-chip package design. With the exhaustive search for improved scaling of microelectronic devices, power supply integrity has become a major concern that is enhanced as supply voltages continue to drop.
Shrinking device dimensions, increased current densities, and increased operating frequencies all have decreased the tolerance for voltage drop and noise. For instance, excessive voltage drops at the point at which power is accessed reduce tolerance for switching speeds and noise margins of a circuit. Additionally, the voltage drops may also inject unwanted noise and/or jitter into the power signal. As a result, voltage drop and unwanted noise in a power supply may lead to functional failures of the design circuit.
Capacitance between power and ground distribution networks help to filter the power supply. For instance, capacitance between power and ground distribution networks act to store charge location, which helps to mitigate the voltage drop and noise of the power supply at supply points. However, in circuit design, including package design, placement and location of the capacitance is very important. Previously, capacitance used to filter an external power supply has been located outside a packaged device. Locating the capacitance outside of the packaged device allows for placement of large capacitances for optimum filtering capabilities, but at a cost. Specifically, capacitance filtering outside of the package is characterized by increased trace lengths which again reduces the integrity of the power supply signal. Trace lengths may be reduced by locating the capacitance on a chip. However, on-chip power supply filtering takes up valuable chip real-estate, and is becomes more costly as the need for improved device scaling continues. As such, attention to power supply integrity is necessary to ensure reliable operation of circuits on a chip.